Light emitting display

ABSTRACT

Embodiments of the present disclosure describe light emitting displays having a light emitter layer that includes an array of light emitters and a wafer having a driving circuit coupled with the light emitter layer, computing devices incorporating the light emitting displays, methods for formation of the light emitting displays, and associated configurations. A light emitting display may include a light emitter layer that includes an array of light emitters and a wafer coupled with the light emitter layer, where the wafer includes a driving circuit formed thereon to drive the light emitters. Other embodiments may be described and/or claimed.

CROSS REFERENCE TO RELATED APPLICATION

The present application is a continuation of U.S. application Ser. No.16/473,983, filed Jun. 26, 2019, entitled “LIGHT EMITTING DISPLAY,”which is a national phase entry under 35 U.S.C. § 371 of InternationalApplication No. PCT/US2017/025111, filed Mar. 30, 2017, entitled “LIGHTEMITTING DISPLAY.” PCT/US2017/025111 designated, among the variousStates, the United States of America. The Specification of thePCT/US2017/025111 Application is hereby incorporated by reference.

TECHNICAL FIELD

The present disclosure relates generally to the field of light emittingdisplays for electronic devices and, more specifically, to lightemitting microdisplays.

BACKGROUND

Legacy approaches to fabricating light emitting displays typically donot provide one or more characteristics such as high pixel density, highbrightness, high contrast, low power operation, and/or compact formfactor that may be desirable in applications such as augmented reality(AR) and/or virtual reality (VR) head mounted displays.

BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments will be readily understood by the following detaileddescription in conjunction with the accompanying drawings. To facilitatethis description, like reference numerals designate like structuralelements. Embodiments are illustrated by way of example, and not by wayof limitation, in the figures of the accompanying drawings.

FIG. 1 schematically illustrates a first wafer assembly having an arrayof light emitters and a second wafer assembly having a driving circuitbefore wafer bonding to form a light emitting display, in accordancewith various embodiments.

FIG. 2 schematically illustrates a light emitting display, in accordancewith various embodiments.

FIG. 3 schematically illustrates a top view of a portion of a lightemitting display, in accordance with various embodiments.

FIGS. 4A and 4B schematically illustrate a cross-sectional side view ofa first wafer assembly having an array of light emitters and a secondwafer assembly having a driving circuit before wafer bonding to form alight emitting display, in accordance with various embodiments.

FIG. 5 schematically illustrates a cross-sectional side view of thewafer assemblies shown in FIGS. 4A-4B after wafer bonding, in accordancewith various embodiments.

FIG. 6 schematically illustrates a cross-sectional side view of thebonded wafer assembly shown in FIG. 5 after removal of layers from thefirst wafer assembly, in accordance with various embodiments.

FIG. 7 schematically illustrates a cross-sectional side view of thebonded wafer assembly shown in FIG. 6 after deposition of a transparentelectrode layer, in accordance with various embodiments.

FIG. 8 schematically illustrates a flow diagram for a process offabricating a light emitting display, in accordance with variousembodiments.

FIG. 9 schematically illustrates a computing device that may include thelight emitting display of FIG. 1, FIG. 2, FIG. 3, and/or FIG. 7, inaccordance with various embodiments.

FIG. 10 is a simplified schematic representation of a head mounteddisplay device that may include the light emitting display of FIG. 1,FIG. 2, FIG. 3, and/or FIG. 7, in accordance with various embodiments.

DETAILED DESCRIPTION

Embodiments herein may include light emitting displays having a lightemitter layer that includes an array of light emitters and a wafercoupled with the light emitter layer, where the wafer includes a drivingcircuit formed thereon to drive the light emitters. In some embodiments,the light emitting display may be a microdisplay formed by wafer bondinga first wafer having a light emitter layer to a second wafer having adriving circuit.

In the following detailed description, reference is made to theaccompanying drawings that form a part hereof, wherein like numeralsdesignate like parts throughout, and in which is shown by way ofillustration embodiments in which the subject matter of the presentdisclosure may be practiced. It is to be understood that otherembodiments may be utilized and structural or logical changes may bemade without departing from the scope of the present disclosure.Therefore, the following detailed description is not to be taken in alimiting sense, and the scope of embodiments is defined by the appendedclaims and their equivalents.

Various operations may be described as multiple discrete actions oroperations in turn, in a manner that is most helpful in understandingthe claimed subject matter. However, the order of description should notbe construed as to imply that these operations are necessarily orderdependent. In particular, these operations may not be performed in theorder of presentation. Operations described may be performed in adifferent order than the described embodiment. Various additionaloperations may be performed and/or described operations may be omittedin additional embodiments.

For the purposes of the present disclosure, the phrase “A and/or B”means (A), (B), or (A and B). For the purposes of the presentdisclosure, the phrase “A, B, and/or C” means (A), (B), (C), (A and B),(A and C), (B and C), or (A, B and C).

The description may use the phrases “in an embodiment,” or “inembodiments,” which may each refer to one or more of the same ordifferent embodiments. Furthermore, the terms “comprising,” “including,”“having,” and the like, as used with respect to embodiments of thepresent disclosure, are synonymous.

The term “coupled with,” along with its derivatives, may be used herein.“Coupled” may mean one or more of the following. “Coupled” may mean thattwo or more elements are in direct physical or electrical contact.However, “coupled” may also mean that two or more elements indirectlycontact each other, but yet still cooperate or interact with each other,and may mean that one or more other elements are coupled or connectedbetween the elements that are said to be coupled with each other.

In various embodiments, the phrase “a first layer formed on a secondlayer” may mean that the first layer is formed over the second layer,and at least a part of the first layer may be in direct contact (e.g.,direct physical and/or electrical contact) or indirect contact (e.g.,having one or more other layers between the first layer and the secondlayer) with at least a part of the second layer.

FIG. 1 schematically illustrates a first wafer assembly 100 having anarray of light emitters 102 and a second wafer assembly 104 having adriving circuit 106, details not shown for clarity, before wafer bondingto form a light emitting display, in accordance with variousembodiments. Arrows between the first wafer assembly 100 and the secondwafer assembly 104 are shown to indicate a placement direction of thefirst wafer assembly 100 on the second wafer assembly 104 during waferbonding, according to some embodiments.

FIG. 2 schematically illustrates a light emitting display 200, inaccordance with various embodiments. In some embodiments, the lightemitting display 200 may include an array of light emitters 202 and adriving circuit 204 that may include a data driver 206, a scan driver208, and drive circuitry, not labeled for clarity, to drive individuallight emitters in the array of light emitters 202. A power source 210may be coupled with the driving circuit 204 in various embodiments. Inembodiments, some or all of the light emitting display 200 may be formedfrom the bonded first wafer assembly 100 and second wafer assembly 104of FIG. 1. In various embodiments, the array of light emitters 202 maycorrespond to the array of light emitters 102 and the driving circuit106 may be included in the driving circuit 204. In some embodiments, thelight emitting display 200 may be a microdisplay having a diagonalmeasurement of less than or equal to approximately 2 inches. In variousembodiments, the light emitting display 200 may have a diagonalmeasurement of less than or equal to approximately 1 inch.

FIG. 3 schematically illustrates a top view of a portion of a lightemitting display 300, in accordance with various embodiments. In someembodiments, the light emitting display 300 may include a display area302 that may include an array of light emitters (e.g., array of lightemitters 102 or 202). In various embodiments, the light emitting display300 may include a first set of interconnects 304 and a second set ofinterconnects 306. In some embodiments, the first set of interconnects304 may be electrically coupled with anodes of the light emitters in thedisplay area 302 and/or the second set of interconnects 306 may beelectrically coupled with cathodes of the light emitters in the displayarea 302. In various embodiments, the first set of interconnects 304 maybe coupled with a first driver (e.g., data driver 206), not shown forclarity, and the second set of interconnects 306 may be coupled with asecond driver (e.g., scan driver 208), not shown for clarity.

In some embodiments, the first driver and/or the second driver may beincluded in drive circuitry (e.g., driving circuit 106 or 204) of awafer bonded to the array of light emitters. In other embodiments, thefirst driver and/or the second driver may be external to the wafer withthe drive circuitry, where the first set of interconnects 304 and/or thesecond set of interconnects 306 may be used to couple the drivecircuitry to one or more drivers that are external to the wafer assembly(e.g., on a separate driver IC). In embodiments, the first set ofinterconnects 304 and/or the second set of interconnects 306 may includemetal pads for connection to one or more integrated circuits external toa wafer assembly that includes the display area 302. In someembodiments, the light emitting display 300 may correspond to a portionof the light emitting display 200 of FIG. 2.

FIGS. 4A and 4B schematically illustrate a cross-sectional side view ofa first wafer assembly 400 having an array of light emitters 402 and asecond wafer assembly 404 having a driving circuit, not shown forclarity, before wafer bonding to form a light emitting display, inaccordance with various embodiments. In some embodiments, the firstwafer 400 may correspond to the first wafer assembly 100 and the secondwafer assembly 404 may correspond to the second wafer assembly 104 ofFIG. 1. In various embodiments, the first wafer assembly 400 may includea wafer 406 that may be a handle wafer, a buffer layer 408 (e.g.,aluminum nitride (AlN), aluminum gallium nitride (AlGaN)), and anucleation layer 410. In some embodiments, the wafer 406 may be a 300millimeter (mm) silicon wafer. However, other materials (e.g., sapphire,silicon carbide, gallium nitride) and/or sizes may be used for the wafer406 in various embodiments. In some embodiments, the array of lightemitters 402 may be included in an interlayer dielectric layer 412. Inembodiments, the interlayer dielectric layer 412 may be an oxide layer.In various embodiments, the first wafer assembly 400 may also includemetal regions 414 that may serve as anodes for light emitters in thearray of light emitters 402. In some embodiments, the metal regions 414may be formed of copper (Cu). However, other metals or other conductivematerials may be used for the metal regions 414 in various embodiments.

In some embodiments, the array of light emitters 402 may include anarray of pixels that may each include more than one light emitter ofdifferent colors, such as a red light emitter 416, a green light emitter418, and a blue light emitter 420. A different number of colors, ordifferent colors, may be used for the pixels in various embodiments. Insome embodiments, the array of light emitters 402 may have greater thanor equal to approximately 2000 pixels per inch (PPI) and in variousembodiments, may have greater than or equal to approximately 3000 PPI.The array of light emitters 402 may have a different PPI in otherembodiments. In some embodiments, the light emitters may be lightemitting diodes (LEDs). In various embodiments, the light emitters maybe monolithically manufactured LEDs. In embodiments, the light emittersmay be organic LEDs. However, other types of LEDs (e.g., micro pyramidsor nanowire LEDs) or other types of light emitters may be used invarious embodiments. In some embodiments, the LED active layers may bemade of Indium Gallium Nitride (InGaN), where differing Indiumcompositions may correspond to different colors. In various embodiments,the blue emitter 420 may have an Indium composition of approximatelybetween 17.8% and 19.5%, the green emitter 418 may have an Indiumcomposition of approximately between 30% and 30.8%., and/or the redemitter 416 may have an Indium composition of approximately between39.6% to 41.2%. In some embodiments, the array of light emitters 402 maybe a micro LED array having a pitch of less than approximately 5micrometers (μm).

In some embodiments, the second wafer assembly 404 may include a wafer430, a first interlayer dielectric layer 432, and a second interlayerdielectric layer 434. In embodiments, the first interlayer dielectriclayer 432 and/or the second interlayer dielectric layer 434 may be oxidelayers. In various embodiments, vias 436 may run through the firstinterlayer dielectric layer 432 and/or metal regions 438 may be locatedin the second interlayer dielectric layer 434. In some embodiments, themetal regions 438 may be formed of copper (Cu). However, other metals orother conductive materials may be used for the metal regions 438 invarious embodiments. In some embodiments, the wafer 430 may be a 300 mmSilicon wafer. However, other sizes and/or types of materials (e.g.,sapphire, silicon carbide, gallium nitride) may be used for the wafer430 in various embodiments. In various embodiments, the wafer 430 may beprepared with driver circuit arrays, not shown for clarity, thatcorrespond to the array of light emitters 402 (e.g., micro LED arrays)on the first wafer 406. In some embodiments, the driver circuit arraysmay be formed of complementary metal oxide semiconductor (CMOS) devices(e.g., in a 22 nanometer (nm) node, 32 nm node, 45 nm node, 65 nm node,130 nm node, or 180 nm node). In other embodiments, the driver circuitarrays may be formed of devices using thin film transistor (TFT)technology or some other device fabrication technology.

FIG. 5 schematically illustrates a cross-sectional side view of thewafer assemblies 400 and 404 shown in FIG. 4 after wafer bonding to forma bonded wafer assembly 440, in accordance with various embodiments. Insome embodiments, the first wafer assembly 400 may be bonded to thesecond wafer assembly 404 using a wafer bonding process such that thedriver circuit arrays of the second wafer assembly 404 are aligned withthe array of light emitters 402 of the first wafer assembly 400. Invarious embodiments, the metal regions 414 of the first wafer assembly400 may be aligned with the metal regions 438 of the second waferassembly 404. In various embodiments, the first wafer assembly 400 maybe bonded to the second wafer assembly 404 such that metal to metalbonds are formed between the metal regions 414 and the metal regions438. In some embodiments, the metal to metal bonds may be copper tocopper bonds. In some embodiments, the first wafer assembly 400 and thesecond wafer assembly 404 may be aligned with an alignment accuracy ofless than or equal to approximately 5 μm.

FIG. 6 schematically illustrates a cross-sectional side view of thebonded wafer assembly 440 shown in FIG. 5 after removal of layers fromthe first wafer assembly 400 to form a bonded wafer assembly 444, inaccordance with various embodiments. As shown, the wafer 406, the buffer408, and the nucleation layer 410 have been removed in accordance withsome embodiments. In other embodiments, a different number or type oflayers may be removed. In some embodiments, the array of light emitters402 may be exposed in the bonded wafer assembly 444 such that they mayemit light in a direction away from the wafer 430.

FIG. 7 schematically illustrates a cross-sectional side view of thebonded wafer assembly 444 shown in FIG. 6 after deposition of atransparent electrode layer 450 to form a light emitting display 452, inaccordance with various embodiments. In embodiments, the transparentelectrode layer 450 may include cathodes for the light emitters in thearray of light emitters 402. In some embodiments, the light emittingdisplay 452 may correspond to the light emitting display 200 of FIG. 2.In various embodiments, the bonded wafer assembly 444 may be diced orsingulated in another manner after deposition of the transparentelectrode layer 450 to obtain one or more light emitting displays 452from the bonded wafer assembly 444.

FIG. 8 schematically illustrates a flow diagram for a process 480 offabricating a light emitting display (e.g., light emitting display 200of FIG. 2 or light emitting display 452 of FIG. 7), in accordance withvarious embodiments. In some embodiments, at a block 482, the process480 may include bonding a light emitter wafer assembly (e.g., waferassembly 100 or 400) having a handle wafer (e.g., wafer 406) and a lightemitter layer (e.g., interlayer dielectric layer 412 with array of lightemitters 402) formed thereon to a second wafer (e.g., wafer 430) thatincludes a driving circuit to drive the light emitter layer. In variousembodiments, the light emitter wafer assembly may be bonded to thesecond wafer using a wafer bonding process. At a block 484, the process480 may include removing the handle wafer (e.g., wafer 406), inaccordance with some embodiments (e.g., using a polishing and/or wetetch process). In various embodiments, the process 480 may includeremoving a nucleation layer (e.g., nucleation layer 410) at a block 486.In some embodiments, at a block 488, the process 482 may includeremoving a buffer layer (e.g., buffer layer 408). At a block 490, theprocess 480 may include depositing a transparent electrode layer (e.g.,transparent electrode layer 450) on the light emitter layer.

FIG. 9 schematically illustrates a computing device 500 that may includethe light emitting display of FIG. 1, the light emitting display 200 ofFIG. 2, the light emitting display 300 of FIG. 3, and/or the lightemitting display 452 of FIG. 7, in accordance with various embodiments.The computing device 500 may be, for example, an AR headset, a VRheadset, a mobile communication device or a desktop or rack-basedcomputing device. The computing device 500 may house a board such as amotherboard 502. The motherboard 502 may include a number of components,including (but not limited to) a processor 504 and at least onecommunication chip 506.

The computing device 500 may include a storage device 508 that may becoupled with the processor 504 and/or other components of the computingdevice 500. In some embodiments, the storage device 508 may include oneor more solid state drives. Examples of storage devices that may beincluded in the storage device 508 include volatile memory (e.g.,dynamic random access memory (DRAM)), non-volatile memory (e.g.,read-only memory, ROM), flash memory, and mass storage devices (such ashard disk drives, compact discs (CDs), digital versatile discs (DVDs),and so forth).

Depending on its applications, the computing device 500 may includeother components that may or may not be physically and electricallycoupled to the motherboard 502. These other components may include, butare not limited to, a graphics processor 510, a digital signalprocessor, a crypto processor, a chipset, an antenna, a display, atouchscreen display, a touchscreen controller, a battery, an audiocodec, a video codec, a power amplifier, a global positioning system(GPS) device, a compass, a Geiger counter, an accelerometer, agyroscope, a speaker, and a camera.

The communication chip 506 and the antenna may enable wirelesscommunications for the transfer of data to and from the computing device500. The term “wireless” and its derivatives may be used to describecircuits, devices, systems, methods, techniques, communicationschannels, etc., that may communicate data through the use of modulatedelectromagnetic radiation through a non-solid medium. The term does notimply that the associated devices do not contain any wires, although insome embodiments they might not. The communication chip 506 mayimplement any of a number of wireless standards or protocols, includingbut not limited to Institute for Electrical and Electronic Engineers(IEEE) standards including Wi-Fi (IEEE 802.11 family), IEEE 802.16standards (e.g., IEEE 802.16-2005 Amendment), Long-Term Evolution (LTE)project along with any amendments, updates, and/or revisions (e.g.,advanced LTE project, ultra mobile broadband (UMB) project (alsoreferred to as “3GPP2”), etc.). IEEE 802.16 compatible broadbandwireless access (BWA) networks are generally referred to as WiMAXnetworks, an acronym that stands for Worldwide Interoperability forMicrowave Access, which is a certification mark for products that passconformity and interoperability tests for the IEEE 802.16 standards. Thecommunication chip 506 may operate in accordance with a Global Systemfor Mobile Communications (GSM), General Packet Radio Service (GPRS),Universal Mobile Telecommunications System (UMTS), High Speed PacketAccess (HSPA), Evolved HSPA (E-HSPA), or LTE network. The communicationchip 506 may operate in accordance with Enhanced Data for GSM Evolution(EDGE), GSM EDGE Radio Access Network (GERAN), Universal TerrestrialRadio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). Thecommunication chip 506 may operate in accordance with Code DivisionMultiple Access (CDMA), Time Division Multiple Access (TDMA), DigitalEnhanced Cordless Telecommunications (DECT), Evolution-Data Optimized(EV-DO), derivatives thereof, as well as any other wireless protocolsthat are designated as 3G, 4G, 5G, and beyond. The communication chip506 may operate in accordance with other wireless protocols in otherembodiments.

The computing device 500 may include a plurality of communication chips506. For instance, a first communication chip 506 may be dedicated toshorter range wireless communications such as Wi-Fi and Bluetooth, and asecond communication chip 506 may be dedicated to longer range wirelesscommunications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, andothers. In some embodiments, the communication chip 506 may supportwired communications. For example, the computing device 500 may includeone or more wired servers.

The processor 504 and/or the communication chip 506 of the computingdevice 500 may include one or more dies or other components in an ICpackage. Such an IC package may be coupled with an interposer or anotherpackage. The term “processor” may refer to any device or portion of adevice that processes electronic data from registers and/or memory totransform that electronic data into other electronic data that may bestored in registers and/or memory. In various embodiments, the computingdevice 500 may include a display 520 that may correspond to the lightemitting display of FIG. 1, the light emitting display 200 of FIG. 2,the light emitting display 300 of FIG. 3, and/or the light emittingdisplay 452 of FIG. 7. In some embodiments, the display 520 may becoupled with the processor 504 and/or the graphics processor 510,connections not shown for clarity. In some embodiments, the display 520may be coupled with the processor 504 via the graphics processor 510. Insome embodiments, a driving circuit (e.g., driving circuit 106 or 204)of the display 520 may be coupled with the processor 502 and/or thegraphics processor 510. In some embodiments, the computing device 500may include one or more of the components or a subset of the componentsshown in FIG. 9.

In various implementations, the computing device 500 may be a laptop, anetbook, a notebook, an ultrabook, a smartphone, a tablet, a personaldigital assistant (PDA), an ultra mobile PC, a mobile phone, a desktopcomputer, a server, a printer, a scanner, a monitor, a set-top box, anentertainment control unit, a digital camera, a portable music player,or a digital video recorder. In further implementations, the computingdevice 500 may be any other electronic device that processes data andincludes or is communicatively coupled with a display device inaccordance with embodiments described herein, for example, a headmounted display device described below.

FIG. 10 is a simplified schematic representation of a head mounteddisplay device 600 that may include the light emitting display 200 ofFIG. 2, the light emitting display 300 of FIG. 3, the light emittingdisplay 452 of FIG. 7, and/or the display 520 of FIG. 9, in accordancewith various embodiments. In some embodiments, the head mounted displaydevice 600 may include a mount 602 to be positioned on a head of a user,a first light emitting display 604, and a second light emitting display606 that may be coupled with the mount 602 such that the light emittingdisplays are to be positioned proximate to a user's eyes when the mount602 is positioned on the user's head. In some embodiments, the mount 602may be included in the frame of a pair of glasses, a pair of goggles, avisor, or some other head mounted display device. In some embodiments, adifferent number of light emitting displays may be used. In variousembodiments, an electronics module 608 may be coupled with and/or insignal communication with the first light emitting display 604 and thesecond light emitting display 606. In some embodiments, the electronicsmodule 608 may include processing and/or communication components suchas some or all of those described with respect to the computing device500 of FIG. 9 (e.g., processor 504, communication chip 506, storagedevice 508, graphics processor 510) and/or a power supply such as abattery. In various embodiments, the head mounted display device 600 mayinclude a single light emitting display rather than individual lightemitting displays for each eye. In some embodiments, the head mounteddisplay device 600 may be in signal communication with a computingdevice such as the computing device 500 and/or may serve as a displaydevice for the computing device.

The following paragraphs provide examples of various ones of theembodiments disclosed herein.

Example 1 may include a light emitting display apparatus comprising: alight emitter layer that includes an array of light emitters; and awafer coupled with the light emitter layer, wherein the wafer includes adriving circuit formed thereon to drive the light emitters.

Example 2 may include the subject matter of Example 1, furthercomprising a first dielectric layer bonded with the light emitter layerhaving a first plurality of metal regions formed therein, wherein thelight emitter layer is formed in a second dielectric layer having asecond plurality of metal regions formed therein, wherein more than onemetal region of the first plurality of metal regions is coupled with acorresponding metal region of the second plurality of metal regions.

Example 3 may include the subject matter of Example 2, wherein the metalregions in the second plurality of metal regions are anodes for thearray of light emitters.

Example 4 may include the subject matter of any one of Examples 1-3,wherein the light emitter layer includes a transparent electrode layer.

Example 5 may include the subject matter of any one of Examples 1-4,wherein the light emitters are light emitting diodes.

Example 6 may include the subject matter of Example 5, wherein the lightemitting diodes have Indium Gallium Nitride active layers.

Example 7 may include the subject matter of any one of Examples 1-6,wherein the light emitting display apparatus is a computing devicefurther comprising a processor coupled with the driving circuit.

Example 8 may include the subject matter of any one of Examples 1-7,wherein the driving circuit is formed with complementary metal oxidesemiconductor (CMOS) transistors or thin film transistors (TFTs).

Example 9 may include the subject matter of any one of Examples 1-8,wherein the array of light emitters has a pitch of less than or equal to5 micrometers and the wafer is a silicon, sapphire, silicon carbide, orgallium nitride wafer.

Example 10 may include a method comprising: bonding a light emitterwafer having a handle wafer and a light emitter layer formed thereon toa second wafer that includes a driving circuit to drive the lightemitter layer; and removing the handle wafer.

Example 11 may include the subject matter of Example 10, wherein thelight emitter wafer includes a buffer layer and the method furthercomprises removing the buffer layer.

Example 12 may include the subject matter of any one of Examples 10-11,wherein the light emitter wafer includes a nucleation layer and themethod further comprises removing the nucleation layer.

Example 13 may include the subject matter of any one of Examples 10-12,further comprising depositing a transparent electrode layer on the lightemitter layer.

Example 14 may include the subject matter of Example 13, wherein thetransparent electrode layer is a cathode layer.

Example 15 may include the subject matter of any one of Examples 10-14,wherein the light emitter layer includes an array of light emittingdiodes in a dielectric layer.

Example 16 may include the subject matter of any one of Examples 10-15,wherein the driving circuit is formed with complementary metal oxidesemiconductor (CMOS) transistors or thin film transistors (TFTs).

Example 17 may include the subject matter of any one of Examples 10-16,wherein the light emitter layer is formed in a first dielectric layerhaving a first plurality of metal regions formed therein, the secondwafer includes a second dielectric layer having a second plurality ofmetal regions formed therein, and wherein bonding the light emitterwafer to the second wafer includes bonding more than one metal region ofthe first plurality of metal regions with a corresponding metal regionof the second plurality of metal regions.

Example 18 may include the subject matter of any one of Examples 10-17,wherein the light emitter wafer includes an array of light emitters thathave a pitch of less than or equal to 5 micrometers.

Example 19 may include a head mounted display device comprising: a mountto be positioned on a head of a user; and a light emitting displaycoupled with the mount such that the light emitting display is to bepositioned proximate the user's eyes when the mount is positioned on theuser's head, wherein the light emitting display includes: a lightemitter layer that includes an array of light emitters; and a wafercoupled with the light emitter layer, wherein the wafer includes adriving circuit formed thereon to drive the light emitters.

Example 20 may include the subject matter of Example 19, furthercomprising a first dielectric layer bonded with the light emitter layerhaving a first plurality of metal regions formed therein, wherein thelight emitter layer is formed in a second dielectric layer having asecond plurality of metal regions formed therein, wherein more than onemetal region of the first plurality of metal regions is coupled with acorresponding metal region of the second plurality of metal regions.

Example 21 may include the subject matter of any one of Examples 19-20,wherein the array of light emitters has a pitch of less than or equal to5 micrometers.

Example 22 may include the subject matter of any one of Examples 19-21,wherein the light emitters are light emitting diodes having IndiumGallium Nitride active layers.

Example 23 may include the subject matter of any one of Examples 19-22,wherein the light emitter layer includes a transparent electrode layerand the driving circuit is formed with complementary metal oxidesemiconductor (CMOS) transistors or thin film transistors (TFTs).

Example 24 may include the subject matter of any one of Examples 19-23,wherein the head mounted display device is an augmented reality displaydevice.

Example 25 may include the subject matter of any one of Examples 19-23,wherein the head mounted display device is a virtual reality displaydevice.

What is claimed is:
 1. A display apparatus comprising: a firstsubstrate, the first substrate comprising: a first dielectric layer; alight emitter layer on the first dielectric layer, wherein the lightemitter layer includes an array of light emitters; wherein the lightemitter layer comprises indium; and a first plurality of metal regionsdisposed in the first dielectric layer, wherein each of the firstplurality of metal regions is disposed underneath, and coupled with,respective light emitters of the array of light emitters; and a secondsubstrate disposed on the first substrate, the second substratecomprising: a second dielectric layer; a plurality of vias providedthrough the second dielectric layer; a third dielectric layer on thesecond dielectric layer; a second plurality of metal regions disposed inthe third dielectric layer, wherein each of the plurality of vias iscoupled with a respective one of the second plurality of metal regions;and circuitry to drive the array of light emitters, wherein the firstsubstrate is bonded to the second substrate such that each of the firstplurality of metal regions is coupled with a respective one of thesecond plurality of metal regions through metal-to-metal bonds.
 2. Thedisplay apparatus of claim 1, wherein the light emitter layer furthercomprises at least one of gallium or nitrogen.
 3. The display apparatusof claim 1, wherein the light emitter layer comprises indium, galliumand nitrogen.
 4. The display apparatus of claim 1, wherein the secondsubstrate further comprises at least one of silicon or aluminum.
 5. Thedisplay apparatus of claim 1, wherein the second substrate furthercomprises a fourth dielectric layer including aluminum and nitrogen. 6.The display apparatus of claim 1, wherein the light emitter layerincludes a transparent electrode layer.
 7. The display apparatus ofclaim 1, wherein the light emitters comprises diodes.
 8. The displayapparatus of claim 1, wherein the circuitry comprises complementarymetal oxide semiconductor (CMOS) transistors or thin film transistors(TFTs).
 9. The display apparatus of claim 1, wherein at least two LEDsof the array of LEDs are spaced within 5 micrometers of each other. 10.A display system comprising: a mount to be positioned on a head of auser; and a display coupled to the mount, wherein the display includes:a first substrate, wherein the first substrate includes: a firstdielectric layer; a light emitter layer on the first dielectric layer,wherein the light emitter layer includes an array of light emitters;wherein the light emitter layer comprises indium; and a first pluralityof metal regions disposed in the first dielectric layer, wherein each ofthe first plurality of metal regions is disposed underneath, and coupledwith, respective light emitters of the array of light emitters; and asecond substrate disposed on the first substrate, wherein the secondsubstrate includes: a second dielectric layer; a plurality of viasprovided through the second dielectric layer; a third dielectric layeron the second dielectric layer; a second plurality of metal regionsdisposed in the third dielectric layer, wherein each of the plurality ofvias is coupled with a respective one of the second plurality of metalregions; and circuitry to drive the array of light emitters, wherein thefirst substrate is bonded to the second substrate such that each of thefirst plurality of metal regions is coupled with a respective one of thesecond plurality of metal regions through metal-to-metal bonds.
 11. Thedisplay system of claim 10, wherein the light emitter layer furthercomprises at least one of gallium or nitrogen.
 12. The display system ofclaim 10, wherein the light emitter layer comprises indium, gallium andnitrogen.
 13. The display system of claim 10, wherein the secondsubstrate further comprises at least one of silicon or aluminum.
 14. Thedisplay system of claim 10, wherein the second substrate furthercomprises a fourth dielectric layer including aluminum and nitrogen. 15.The display system of claim 10, wherein at least two LEDs of the arrayof LEDs are spaced within 5 micrometers of each other.
 16. An apparatuscomprising: a first substrate comprising: an array of light emittingdiodes (LEDs), wherein the LEDs comprise indium, gallium, and nitrogen;and a layer coupled to the array of LEDs, the layer comprising aluminumand nitrogen; and a second substrate bonded to the first substrate,wherein the second substrate includes circuitry conductively coupled tothe array of LEDs, wherein the circuitry comprises complementary metaloxide semiconductor (CMOS) transistors or thin film transistors (TFTs).17. The apparatus of claim 16, wherein a layer is a first layer, whereinthe second substrate further includes a second layer comprising aluminumand nitrogen.
 18. The apparatus of claim 16, wherein the first substratefurther comprises a transparent electrode layer coupled to the array ofLEDs.
 19. The apparatus of claim 16, wherein one or both of the firstsubstrate and the second substrate comprises one of silicon, aluminumand oxygen, silicon and carbon, or gallium and nitrogen.
 20. Theapparatus of claim 16, wherein at least two LEDs of the array of LEDsare spaced within 5 micrometers of each other.